1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for manufacturing this semiconductor memory device. More particularly, the present invention relates to a MOS-type semiconductor memory device having a multivalued memory in a planar cell structure and a method for manufacturing this MOS-type semiconductor memory device.
2. Description of the Related Art
A memory cell structure of a mask ROM memory device used at present is constructed by one memory cell with respect to one bit. In this memory device, when a gate voltage of a memory cell transistor is set to a high potential, whether or not an electric current flows between a source and a drain of the memory cell transistor corresponds to value "1" or "0", or value "0" or "1", thereby reading data. There are various kinds of writing systems of ROM data such as a field system, a depression system, a core system and a contact system. In each of these systems, one bit corresponds to one memory cell.
Degree of integration in the semiconductor memory device is improved every year so that an area required for one memory cell is reduced. In the case of a mask ROM, an area for one memory transistor is reduced by reducing the area for a memory cell. A reduction in size of a memory cell has been tried by using a minimum design rule at any time.
One epoch-making method for reducing an area for a memory cell section is a method using a memory cell structure called a planar structure. For example, this method using the memory cell structure is shown in Japanese Patent Application Laying Open (KOKAI) Nos. 61-288464, 63-96953. The planar cell structure has a continuous diffusive region for a source region of plural MOS transistors, and a continuous diffusive region for a drain region of the plural MOS transistors. The continuous diffusive regions for the source and drain regions are alternately formed on a substrate in parallel with each other. A gate electrode is formed on the substrate such that the gate electrode crosses both the diffusive regions through an insulation film. In the planar cell structure, it is not necessary to dispose a field oxide film for separating constructional elements from each other and the plural transistors commonly have the source and drain regions. Accordingly, it is sufficient to dispose one contact portion between the source and drain regions with respect to several or several ten transistors, which is advantageous in the case of high integration.
However, one bit also corresponds to one memory cell in this planar cell structure.
In another method for reducing an area for a memory cell region, an amount of information per one memory cell is increased by setting the value of an electric current flowing out of one memory cell to three or more kinds of values. Japanese Patent Application Laying Open (KOKAI) No. 59-148360 and No. 63-81858 shows one method for setting this electric current value to three or more kinds of values. In this method, an effective channel width is set to three or more kinds of widths by core implantation into a channel region. For example, a multivalued memory in this proposed method uses a simple method in which a turning-on electric current between the source and the drain is controlled and set to four current values by using a core implantation system.
In the multivalued memory using the core implantation system, a value of the turning-on electric current is greatly dispersed by a shift in overlapping of a mask for the core implantation and a mask of a field oxide film. Therefore, no multivalued memory using the core implantation system is realized in a process for mass production.